1. Field of the Invention
The present invention relates to methods for repairing and operating a memory component and to a memory component, which methods and memory component make it possible to extend refresh times.
2. Description of the Related Art
The reduction of the linear dimensions of memory components, in particular DRAM elements (DRAM=Dynamic Random Access Memory), is reaching physical and economic limits. The ever more extensive reduction of the dimensions of the memory cells and their features requires a very high technical outlay that is continuing to rise. One example is the introduction of dielectrics having a very high dielectric constant as the dielectric of the storage capacitor.
The extreme technological outlay is already offsetting a considerable portion of the cost advantage that results from reducing the linear dimensions (shrink). It is customary for the introduction of a DRAM shrink to be associated with an increase of 10% to 15% in the technology costs, while the cost advantage associated with the shrink is typically in the region of 20% to 30%.
Up until now, the capacitance of the capacitor in a DRAM cell has essentially been kept constant from one generation to the next, no more than approximately 50 to 100 individual memory cells on a single DRAM element having to be repaired. This repair operation is effected by replacing the defective regular memory cells with redundant memory cells. However, it is becoming increasingly more difficult to develop cost-effective DRAM technologies which require only 50 to 100 randomly distributed memory cells to be repaired per chip.
In this case, it is primarily defective memory cells which are replaced. Memory cells which have a short circuit or whose data retention time falls below a first predetermined limit value and is thus unacceptably short are defective.
Memory cells which are not defective but whose data retention time is below a second predetermined limit value are referred to below as weak cells. In this case, the number of weak cells is just as dependent on the requirements imposed on the memory cells and the predetermined limit value as it is on the technology. As described above, each shrink increases the number of weak cells.
The higher the proportion of weak cells in the total number of memory cells of a DRAM element or else of an individual memory block on a DRAM element, the more complicated the repair operation becomes. In particular, the number of weak cells on redundant word lines also increases. The risk or likelihood, when repairing or replacing a defective or weak memory cell on a regular word line, of good memory cells on the regular word line that is to be replaced simultaneously being replaced with weak memory cells on the redundant word line consequently increases. The result is that the number of redundant word lines required and thus the chip area required and the production costs increase more than proportionally.
U.S. Pat. No. 6,272,054 B1 describes a memory architecture having an array of twin memory cells, two memory cells respectively being simultaneously connected to a sense amplifier via a respective bit line.
U.S. Pat. No. 6,714,476 B2 describes a DRAM array that can be operated, in an individual-cell operating mode, as an array of individual cells and, in a twin-cell operating mode, as an array of twin cells. Although there is a high storage capacity in the individual-cell operating mode, it has the disadvantages described above. Although these disadvantages are diminished in the twin-cell operating mode, it is necessary to double the chip area in order to achieve the same storage capacity.